The invention relates to a frequency multiplier system and more particularly to a digital frequency multiplier system suitable for handling a varying input frequency signal typically at relatively low frequencies.
In known frequency multiplication systems use is made of phase locked loops or voltage to frequency and frequency to voltage conversion. Phase locked loop (PLL) techniques commonly used for frequency multiplication have certain drawbacks. The principle drawback at low frequencies is the loop response time due to the low pass filter used in the feedback loop of the PLL. This effectively means that at very low input frequencies the frequency produced by the PLL may drift considerably. Also phase locked loops cannot readily cope with high dynamic ranges coupled with high multiplication factors. For these to be correctly implemented high response times are required which are unacceptable. The further disadvantage is that the phase locked loop is essentially an analogue system and this gives a poor performance when the temperature of the system is subject to change.
The other common method of frequency multiplying is to convert the input frequency to an analogue voltage, process this voltage, probably with an op-amp, and then convert this voltage to a higher frequency using a V/F converter. Again problems occur at low frequencies--the Frequency to Voltage (F/V) converter cannot produce a steady voltage output. A large amount of ripple is produced which may be easily eliminated using some form of DC filter technique. In so doing the response time of the system becomes too high and again this is unacceptable. This system is also an analogue system and thus suffers in the same way as PLL's.